The present invention relates to semiconductor memory devices, and more particularly to semiconductor memory devices having a row redundancy circuit for replacing (or substituting) defective normal memory cell(s) in a row with a spare or redundant memory cell to repair the defective memory cells.
As is well known in this technical field, semiconductor memory devices have a plurality of memory cells arranged in rows and columns, i.e., in the form of a matrix. In general, as the semiconductor memory devices have been constructed with arrays having increasingly higher densities, the unit area alloted to individual memory cells has decreased. If a defect is present in even one of the memory cells, the semiconductor memory device cannot be used. Thus, to improve the yield of the semiconductor memory devices, a redundancy technique is commonly employed, whereby defective memory cells are replaced with the reductant memory cells which are provided in the respective rows and columns during fabrication of the semiconductor device. In an early redundancy technique, fuses are connected to each bit line or word line. When a memory cell is found to be defective, the corresponding fuse connected between the bit line or word line and the defective memory cell is opened to thereby cut off the defective memory cell and allow the cell redundancy to be used to replace the defective memory cell.
Unfortunately, as memory cell density for semiconductor memory devices has increased, it has become increasingly inefficient and troublesome to provide fuses for all of the memory cells. Thus, a method of decoding internal address signals for the individual redundant memory cell has been used, particularly where a defective memory cell occurs in semiconductor devices providing row redundancy circuits.
FIG. 1 is a schematic block diagram for a conventional semiconductor device having row redundancy circuits and using an internal address decoding method. In FIG. 1, a normal memory cell array 20L and redundant memory cell array 30L are arranged on the left side. A normal memory cell array 20R and redundant memory cell array 30R are arranged on the right side. Each side is centered on an input/output line 50. Further, the normal memory cell arrays 20L and 20R, and the redundant memory cell arrays 30L and 30R are connected to sense amplifier sections 40L and 40R, respectively. Sense amplifier control circuits 60L and 60R, redundant word line drivers 70L and 70R and fuse boxes 80L and 80R are further provided. Here, each of the sense amplifier sections 40L and 40R includes a bit line equalizing circuit, a sense amplifier composed of a P-type sense amplifier and an N-type sense amplifier, an isolation gate, etc. FIG. 1 shows only two memory arrays taken from the memory device, ad the number of the memory arrays is expandable.
In operation, the redundant memory cell arrays 30L and 30R are selected in response to redundant address signals REDL and REDR supplied from the fuse boxes 80L and 80R, and are enabled in response to the output signals RWLL and RWLR of the redundant word line drivers 70L and 70R, respectively. In other words, if the left normal memory cell array 20L is defective, the left redundant memory cell array 30L is used to repair the defect, and if the right normal memory cell array 20R is defective, the right redundant memory cell array 30R is used to repair the defect. For instance, if an arbitrary memory cell in the left normal memory cell array 20L is defective, a redundant word line corresponding to the defective normal word line is enabled in the redundant memory cell array 30L, and an output of the normal word line driver 90L is disabled in response to the redundant address signal REDL.
Turning now to FIG. 2, the fuse box 80L for programming the defect-generated address for the redundancy is illustrated. Transistors ml to mi receive row address signals and are used to select a memory cell within the memory array by selectively connecting fuses f1 to fi. Transistors A0 and A1 receive block selection address signals and are used to select the memory arrays do not have fuses connected thereto. In the redundancy programming, if the block selection address signals A0 and A1 are held to the "low" level, and the row address signals related to the defective memory cell are entered, the fuses receiving the defective address signals are properly opened (cut off) by, for example, laser beam projection, thereby allowing node n1 to have a "high" level and thus, connecting redundant word line RWL with a signal .PHI.X to enable the redundant word line RWL.
However, in FIG. 2, since the block selection address signals A0 and A1 applied to the fuse box are limited to two, the repair operation is restrictive. This limitation is also shown in FIGS. 3A and 3B, in which the dotted line represents the defective normal word line and the solid line the redundant word line. Accordingly, if the number of defective word lines in a memory cell array is larger than the number of redundant word lines provided in the memory cell array, not all of the defective word lines can be repaired. See FIG. 3B. It also means that a redundant word line belonging to a specific memory cell array cannot replace the defective word line belonging to adjacent memory cell arrays. This is because the adjacent memory cell arrays have a fuse box as shown in FIG. 2, and also because block selection address signals A0 and A1 applied to the fuse box are limited in number. Accordingly, at least one extra fuse box should be provided to increase the yield of memory cells. However, this provision has heretofore placed a heavy burden on attempts to increase memory cell density in semiconductor memory devices. This becomes an even more severe problem since the number of fuse boxes gradually increases as the semiconductor memory device is integrated to larger and larger degrees.